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| LXT9763 Fast Ethernet 10/100 Hex Transceiver with Full MII Datasheet The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock recovery with proprietary Optimal Signal Processing (OSPTM) architecture improves SNR 3 dB over ideal analog filters. All six network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The LXT9763 supports both half- and full-duplex operation at 10 and 100 Mbps. A fully independent Media Independent Interface (MII) for each port provides maximum control for switch and multi-port adapter applications. In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED driver outputs for each port. The LXT9763 requires only a single 3.3V power supply. Applications s 100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs. Product Features s s s s s Six independent IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters. Proprietary Optimal Signal ProcessingTM (OSPTM) architecture improves SNR by 3 dB over ideal analog filters. Baseline wander correction for improved 100BASE-TX performance. 100BASE-FX fiber-optic capability on all ports. Supports both auto-negotiation and legacy systems without auto-negotiation capability. s s s s s s JTAG boundary scan. Six MII ports for independent PHY port operation. Configurable via MDIO port or external control pins. Maskable interrupts. Very low power 3.3V operation (380 mW per channel, typical). 208-pin PQFP (0-70 oC ambient temperature range). As of January 15, 2001, this document replaces the Level One document LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII. Order Number: 249110-001 January 2001 Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT9763 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Contents 1.0 Functional Description...........................................................................................16 1.1 Introduction..........................................................................................................16 1.1.1 OSPTM Architecture ................................................................................16 1.1.2 Comprehensive Functionality .................................................................16 Interface Descriptions..........................................................................................17 1.2.1 10/100 Network Interface .......................................................................17 1.2.2 Twisted-Pair Interface ............................................................................17 1.2.3 Fiber Interface ........................................................................................18 1.2.4 Configuration Management Interface .....................................................18 1.2.5 MDIO Management Interface .................................................................18 MII Addressing ....................................................................................................18 1.3.1 Hardware Control Interface ....................................................................20 1.3.2 MII Data Interface...................................................................................20 Operating Requirements .....................................................................................20 1.4.1 Power Requirements..............................................................................20 Clock Requirements ............................................................................................21 1.5.1 Reference Clock.....................................................................................21 Initialization..........................................................................................................21 1.6.1 Power-Down Mode.................................................................................22 1.6.2 Reset ......................................................................................................22 Hardware Configuration Settings ........................................................................23 Establishing Link .................................................................................................24 1.8.1 Auto-Negotiation.....................................................................................24 MII Operation.......................................................................................................25 1.9.1 Transmit Clock .......................................................................................26 1.9.2 Transmit Enable .....................................................................................26 1.9.3 Receive Data Valid.................................................................................26 1.9.4 Error Signals...........................................................................................26 1.9.5 Carrier Sense .........................................................................................27 1.9.6 Collision..................................................................................................27 1.9.7 Loopback................................................................................................27 100 Mbps Operation............................................................................................28 1.10.1 100BASE-X Network Operations ...........................................................28 1.10.2 100BASE-X Protocol Sublayer Operations ............................................29 10 Mbps Operation..............................................................................................33 1.11.1 10T Preamble Handling..........................................................................34 1.11.2 10T Carrier Sense ..................................................................................34 1.11.3 10T Dribble Bits......................................................................................34 1.11.4 10T Link Test..........................................................................................34 Monitoring Operations .........................................................................................35 1.12.1 Monitoring Auto-Negotiation...................................................................35 1.12.2 Per-Port LED Driver Functions ...............................................................35 Boundary Scan (JTAG1149.1) Functions............................................................36 1.13.1 Boundary Scan Interface........................................................................36 1.13.2 State Machine ........................................................................................36 1.13.3 Instruction Register ................................................................................36 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Datasheet 3 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.13.4 Boundary Scan Register ........................................................................ 37 2.0 Application Information......................................................................................... 38 2.1 Design Recommendations .................................................................................. 38 2.1.1 General Design Guidelines .................................................................... 38 2.1.2 Power Supply Filtering ........................................................................... 38 2.1.3 Power and Ground Plane Layout Considerations .................................. 39 2.1.4 MII Terminations .................................................................................... 39 2.1.5 The RBIAS Pin ....................................................................................... 40 2.1.6 The Twisted-Pair Interface ..................................................................... 40 2.1.7 The Fiber Interface................................................................................. 40 Typical Application Circuits ................................................................................. 41 2.2 3.0 4.0 5.0 Test Specifications.................................................................................................. 44 Register Definitions ................................................................................................ 59 Package Specifications ......................................................................................... 73 4 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 LXT9763 Block Diagram ....................................................................................... 9 LXT9763 Pin Assignments ..................................................................................10 LXT9763 Interfaces ............................................................................................17 Port Address Scheme ........................................................................................19 Management Interface Read Frame Structure ...................................................19 Management Interface Write Frame Structure ...................................................20 Interrupt Logic ....................................................................................................20 Initialization Sequence .......................................................................................22 Hardware Configuration Settings .......................................................................23 Overview of Link Establishment .........................................................................25 MII Data Interface ...............................................................................................26 Loopback Paths ..................................................................................................27 100BASE-X Frame Format ................................................................................28 100BASE-TX Data Path .....................................................................................29 Protocol Sublayers .............................................................................................30 LED Pulse Stretching .........................................................................................36 Power and Ground Supply Connections ............................................................41 Typical Twisted-Pair Interface ............................................................................42 Typical Fiber Interface ........................................................................................43 100BASE-TX Receive Timing (4B Mode) ...........................................................47 100BASE-TX Transmit Timing (4B Mode) .........................................................48 100BASE-TX Receive Timing (5B Mode) ..........................................................49 100BASE-TX Transmit Timing (5B Mode) .........................................................50 100BASE-FX Receive Timing ............................................................................51 100BASE-FX Transmit Timing ...........................................................................52 10BASE-T Receive Timing .................................................................................53 10BASE-T Transmit Timing ................................................................................54 10BASE-T SQE (Heartbeat) Timing ...................................................................54 10BASE-T Jab and Unjab Timing ......................................................................55 Auto Negotiation and Fast Link Pulse Timing ....................................................55 Fast Link Pulse Timing .......................................................................................56 MDIO Write Timing (MDIO Sourced by MAC) ....................................................56 MDIO Read Timing (MDIO Sourced by PHY) ....................................................57 Power-Up Timing ................................................................................................57 RESET And Power-Down Recovery Timing ......................................................58 PHY Identifier Bit Mapping .................................................................................64 LXT9763 Package Specification .........................................................................73 Datasheet 5 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 LXT9763 MII Signal Descriptions........................................................................ 11 LXT9763 Network Interface Signal Descriptions................................................. 13 LXT9763 Miscellaneous Signal Descriptions ...................................................... 13 LXT9763 Power Supply Signal Descriptions....................................................... 14 LXT9763 JTAG Test Signal Descriptions............................................................ 14 LXT9763 LED Signal Descriptions...................................................................... 15 Hardware Configuration Settings ........................................................................ 23 Carrier Sense, Loopback, and Collision Conditions............................................ 28 4B/5B Coding ...................................................................................................... 30 BSR Mode of Operation ...................................................................................... 37 Supported JTAG Instructions .............................................................................. 37 Device ID Register .............................................................................................. 37 Magnetics Requirements .................................................................................... 40 Absolute Maximum Ratings ................................................................................ 44 Operating Conditions .......................................................................................... 44 Digital I/O Characteristics 1................................................................................. 44 Digital I/O Characteristics - MII Pins ................................................................... 45 Required Reference Clock (REFCLK) Characteristics........................................ 45 100BASE-TX Transceiver Characteristics .......................................................... 45 100BASE-FX Transceiver Characteristics .......................................................... 46 10BASE-T Transceiver Characteristics............................................................... 46 100BASE-TX Receive Timing Parameters (4B Mode)........................................ 47 100BASE-TX Transmit Timing Parameters (4B Mode)....................................... 48 100BASE-TX Receive Timing Parameters (5B Mode)........................................ 49 100BASE-TX Transmit Timing Parameters (5B Mode)....................................... 50 100BASE-FX Receive Timing Parameters ......................................................... 51 100BASE-FX Transmit Timing Parameters ........................................................ 52 10BASE-T Receive Timing Parameters.............................................................. 53 10BASE-T Transmit Timing Parameters............................................................. 54 10BASE-T SQE (Heartbeat) Timing Parameters ................................................ 55 10BASE-T Jab and Unjab Timing Parameters.................................................... 55 Auto Negotiation and Fast Link Pulse Timing Parameters.................................. 56 MDIO Timing Parameters ................................................................................... 57 Power-Up Timing Parameters............................................................................ 57 RESET and Power-Down Recovery Timing Parameters ................................... 58 Register Set ........................................................................................................ 59 Register Bit Map.................................................................................................. 60 Control Register (Address 0)............................................................................... 62 Status Register (Address 1) ................................................................................ 62 PHY Identification Register 1 (Address 2)........................................................... 63 PHY Identification Register 2 (Address 3)........................................................... 64 Auto Negotiation Advertisement Register (Address 4)........................................ 64 Auto Negotiation Link Partner Base Page Ability Register (Address 5) .............. 65 Auto Negotiation Expansion (Address 6) ............................................................ 66 Auto Negotiation Next Page Transmit Register (Address 7) ............................... 67 Auto Negotiation Link Partner Next Page Receive Register (Address 8) ........... 67 Port Configuration Register (Address 16, Hex 10) .............................................. 68 Quick Status Register (Address 17, Hex 11) ...................................................... 68 Interrupt Enable Register (Address 18, Hex 12) ................................................. 69 6 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 50 51 52 53 Interrupt Status Register (Address 19, Hex 13) ..................................................70 LED Configuration Register (Address 20, Hex 14)..............................................71 Transmit Control Register #1 (Address 28).........................................................72 Transmit Control Register #2 (Address 30).........................................................72 Datasheet 7 Revision History Revision Date Description Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 1. LXT9763 Block Diagram RESET CFG<2:0> ADD<4:0> MDIO MDC MDINT Management / Mode Select Logic Global Functions Clock Generator VCC Pwr Supply GND REFCLK Register Set TX_ENn TX PCS TXDn_<3:0> TX_ERn TX_CLKn Parallel/Serial Converter Manchester 10 Encoder Scrambler 100 & Encoder Auto Negotiation Register Set OSPTM Pulse Shaper TP Driver + + TPFOP n TP / Fiber Out TPFON n ECL Driver ED/CFGn_<3:0> Collision Detect OSPTM COLn Clock Generator Media Select Adaptive EQ with BaseLine Wander Cancellation + 100TX RX_CLKn RXDn_<3:0> RXDVn CRSn RX_ERn RX PCS Carrier Sense Data Valid Error Detect Serial to Parallel Converter 10 100 Manchester Decoder Decoder & Descrambler + OSPTM Slicer 10BT 100FX TP / Fiber In TPFIP n TPFIN n + PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 Per-Port Functions - Datasheet 9 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 2. LXT9763 Pin Assignments GNDD ....... 1 RX_ER4/RXD4_4 ....... 2 TX_ER4/TXD4_4 ....... 3 TX_CLK4 ....... 4 TX_EN4 ....... 5 TXD4_0 ....... 6 TXD4_1 ....... 7 TXD4_2 ....... 8 TXD4_3 ....... 9 COL4 ....... 10 CRS4 ....... 11 RXD3_3 ....... 12 RXD3_2 ....... 13 RXD3_1 ....... 14 VCCIO ....... 15 GNDD ....... 16 RXD3_0 ....... 17 RX_DV3 ....... 18 RX_CLK3 ....... 19 RX_ER3/RXD3_4 ....... 20 TX_ER3/TXD3_4 ....... 21 TX_CLK3 ....... 22 TX_EN3 ....... 23 TXD3_0 ....... 24 TXD3_1 ....... 25 TXD3_2 ....... 26 TXD3_3 ....... 27 COL3 ....... 28 CRS3 ....... 29 RXD2_3 ....... 30 VCCIO ....... 31 GNDD ....... 32 RXD2_2 ....... 33 RXD2_1 ....... 34 RXD2_0 ....... 35 RX_DV2 ....... 36 RX_CLK2 ....... 37 RX_ER2/RXD2_4 ....... 38 TX_ER2/TXD2_4 ....... 39 TX_CLK2 ....... 40 TX_EN2 ....... 41 TXD2_0 ....... 42 TXD2_1 ....... 43 TXD2_2 ....... 44 TXD2_3 ....... 45 COL2 ....... 46 CRS2 ....... 47 RXD1_3 ....... 48 RXD1_2 ....... 49 RXD1_1 ....... 50 RXD1_0 ....... 51 VCCIO ....... 52 208 ..........VCCIO 207 ..........RX_CLK4 206 ..........RX_DV4 205 ..........RXD4_0 204 ..........RXD4_1 203 ..........RXD4_2 202 ..........RXD4_3 201 ..........CRS5 200 ..........COL5 199 ..........TXD5_3 198 ..........TXD5_2 197 ..........TXD5_1 196 ..........TXD5_0 195 ..........TX_EN5 194 ..........TX_CLK5 193 ..........VCCIO 192 ..........GNDD 191 ..........TX_ER5/TXD5_4 190 ..........RX_ER5/RXD5_4 189 ..........RX_CLK5 188 ..........RX_DV5 187 ..........RXD5_0 186 ..........RXD5_1 185 ..........RXD5_2 184 ..........RXD5_3 183 ..........LED/CFG0_3 182 ..........LED/CFG0_2 181 ..........LED/CFG0_1 180 ..........LED/CFG1_3 179 ..........VCCD 178 ..........GNDD 177 ..........LED/CFG1_2 176 ..........LED/CFG1_1 175 ..........LED/CFG2_3 174 ..........LED/CFG2_2 173 ..........LED/CFG2_1 172 ..........LED/CFG3_3 171 ..........LED/CFG3_2 170 ..........LED/CFG3_1 169 ..........LED/CFG4_3 168 ..........LED/CFG4_2 167 .......... TRST 166 ..........TCK 165 ..........TMS 164 ..........TDO 163 ..........TDI 162 ..........LED/CFG4_1 161 ..........LED/CFG5_3 160 ..........LED/CFG5_2 159 ..........LED/CFG5_1 158 ..........GNDA 157 ..........TPFIP5 Part # LOT # FPO # LXT9763 XX XXXXXX XXXXXXXX Rev # 156.......... TPFIN5 155.......... VCCR 154.......... VCCT 153.......... TPFOP5 152.......... TPFON5 151.......... GNDA 150.......... GNDA 149.......... TPFON4 148.......... TPFOP4 147.......... VCCT 146.......... VCCR 145.......... TPFIN4 144.......... TPFIP4 143.......... GNDA 142.......... GNDA 141.......... TPFIP3 140.......... TPFIN3 139.......... VCCR 138.......... VCCT 137.......... TPFOP3 136.......... TPFON3 135.......... GNDA 134.......... N/C 133.......... N/C 132.......... N/C 131.......... N/C 130.......... N/C 129.......... N/C 128.......... N/C 127.......... N/C 126.......... GNDA 125.......... TPFON2 124.......... TPFOP2 123.......... VCCT 122.......... VCCR 121.......... TPFIN2 120.......... TPFIP2 119.......... GNDA 118.......... GNDA 117.......... TPFIP1 116.......... TPFIN1 115.......... VCCR 114.......... VCCT 113.......... TPFOP1 112.......... TPFON1 111.......... GNDA 110.......... GNDA 109.......... TPFON0 108.......... TPFOP0 107.......... VCCT 106.......... VCCR 105.......... TPFIN0 Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT9763 is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order. 10 GNDD .......53 RX_DV1 .......54 RX_CLK1 .......55 RX_ER1/RXD1_4 .......56 TX_ER1/TXD1_4 .......57 TX_CLK1 .......58 TX_EN1 .......59 TXD1_0 .......60 TXD1_1 .......61 TXD1_2 .......62 TXD1_3 .......63 COL1 .......64 CRS1 .......65 RXD0_3 .......66 VCCIO .......67 GNDD .......68 RXD0_2 .......69 RXD0_1 .......70 RXD0_0 .......71 RX_DV0 .......72 RX_CLK0 .......73 RX_ER0/RXD0_4 .......74 TX_ER0/TXD0_4 .......75 TX_CLK0 .......76 TX_EN0 .......77 GNDS .......78 TXD0_0 .......79 VCCD .......80 GNDD .......81 TXD0_1 .......82 TXD0_2 .......83 TXD0_3 .......84 COL0 .......85 CRS0 .......86 GNDD .......87 GNDD .......88 VCCD .......89 MDINT .......90 TXSLEW_0 .......91 REFCLK .......92 RESET .......93 TXSLEW_1 .......94 MDC .......95 MDIO .......96 ADD_0 .......97 ADD_1 .......98 ADD_2 .......99 ADD_3 .......100 ADD_4 .......101 RBIAS .......102 GNDA .......103 TPFIP0 .......104 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 1. Pin# LXT9763 MII Signal Descriptions Symbol Type1 Data Interface Pins Signal Description2 79 82 83 84 60 61 62 63 42 43 44 45 24 25 26 27 6 7 8 9 196 197 198 199 77 59 41 23 5 195 75 57 39 21 3 191 76 58 40 22 4 194 71 70 69 66 TXD0_0 TXD0_1 TXD0_2 TXD0_3 TXD1_0 TXD1_1 TXD1_2 TXD1_3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXD3_0 TXD3_1 TXD3_2 TXD3_3 TXD4_0 TXD4_1 TXD4_2 TXD4_3 TXD5_0 TXD5_1 TXD5_2 TXD5_3 TX_EN0 TX_EN1 TX_EN2 TX_EN3 TX_EN4 TX_EN5 TX_ER0/TXD0_4 TX_ER1/TXD1_4 TX_ER2/TXD2_4 TX_ER3/TXD3_4 TX_ER4/TXD4_4 TX_ER5/TXD5_4 TX_CLK0 TX_CLK1 TX_CLK2 TX_CLK3 TX_CLK4 TX_CLK5 RXD0_0 RXD0_1 RXD0_2 RXD0_3 I Transmit Data - Port 0. 4-bit parallel data to be transmitted from port 0 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. Transmit Data - Port 1. 4-bit parallel data to be transmitted from port 1 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. Transmit Data - Port 2. 4-bit parallel data to be transmitted from port 2 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. Transmit Data - Port 3. 4-bit parallel data to be transmitted from port 3 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. Transmit Data - Port 4. 4-bit parallel data to be transmitted from port 4 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. Transmit Data - Port 5. 4-bit parallel data to be transmitted from port 5 is clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error signal is re-mapped to provide a fifth data bit. I I I I I I Transmit Enable - Ports 0 - 5. Active High input enables respective port transmitter. This signal must be synchronous to the TX_CLK. I Transmit Coding Error - Ports 0 - 5. Valid during 100 Mbps operation only. This signal must be driven synchronously to TX_CLK. When High, forces the respective port to transmit Halt (H) code group. Transmit Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these signals are re-mapped to provide the fifth data bit (TXDn_4) for their respective ports (n). Transmit Clock - Ports 0 - 5. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps operation. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT9763 samples these signals on the rising edge of TX_CLK. O O Receive Data - Port 0. Data received at network port 0 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet 11 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 1. Pin# 51 50 49 48 35 34 33 30 17 14 13 12 205 204 203 202 187 186 185 184 86 65 47 29 11 201 85 64 46 28 10 200 72 54 36 18 206 188 74 56 38 20 2 190 73 55 37 19 207 189 LXT9763 MII Signal Descriptions (Continued) Symbol Type1 Signal Description2 Receive Data - Port 1. Data received at network port 1 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. Receive Data - Port 2. Data received at network port 2 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. Receive Data - Port 3. Data received at network port 3 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. Receive Data - Port 4. Data received at network port 4 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. Receive Data - Port 5. Data received at network port 5 is output in 4-bit parallel nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive error signals are re-mapped to provide a fifth data bit. RXD1_0 RXD1_1 RXD1_2 RXD1_3 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXD3_0 RXD3_1 RXD3_2 RXD3_3 RXD4_0 RXD4_1 RXD4_2 RXD4_3 RXD5_0 RXD5_1 RXD5_2 RXD5_3 CRS0 CRS1 CRS2 CRS3 CRS4 CRS5 COL0 COL1 COL2 COL3 COL4 COL5 RX_DV0 RX_DV1 RX_DV2 RX_DV3 RX_DV4 RX_DV5 RX_ER0/RXD0_4 RX_ER1/RXD1_4 RX_ER2/RXD2_4 RX_ER3/RXD3_4 RX_ER4/RXD4_4 RX_ER5/RXD5_4 RX_CLK0 RX_CLK1 RX_CLK2 RX_CLK3 RX_CLK4 RX_CLK5 O O O O O O Carrier Sense - Ports 0 - 5. On detection of valid carrier (either transmit or receive in half-duplex; receive only in full-duplex), these signals are asserted asynchronously with respect to RX_CLK. CRS is deasserted on loss of carrier, synchronous to RX_CLK. O Collision - Ports 0 - 5. Active High indication of simultaneous receive and transmit activity. These signals are asserted asynchronously with respect to RX_CLK. These signals are inactive during full-duplex operation. O Receive Data Valid - Ports 0 - 5. These signals are synchronous to the respective RX_CLKn. Active High indication that received code group maps to valid data. During 10M operation, RX_DVn is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. Receive Error - Ports 0 - 5. These signals are synchronous to the respective RX_CLK. Active High indicates that received code group is invalid, or that PLL is not locked. O During 10M operation, active High indicates that the received data is invalid (SFD = A2 rather than 5D.) Receive Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these signals are re-mapped to provide the fifth data bit (RXDn_4) for their respective ports. O Receive Clock - Ports 0 - 5. This continuous recovered clock provides the reference for RXD, RX_DV and RX_ER signals. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). 12 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 1. Pin# LXT9763 MII Signal Descriptions (Continued) Symbol Type1 Signal Description2 MII Control Interface Pins 95 96 90 MDC MDIO MDINT I I/O OD Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates status change. Interrupt is cleared by reading Register 19. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Table 2. Pin# 108, 109 113, 112 124, 125 137, 136 148, 149 153, 152 104, 105 117, 116 120, 121 141, 140 144, 145 157, 156 LXT9763 Network Interface Signal Descriptions Symbol TPFOP0, TPFON0 TPFOP1, TPFON1 TPFOP2, TPFON2 TPFOP3, TPFON3 TPFOP4, TPFON4 TPFOP5, TPFON5 TPFIP0, TPFIN0 TPFIP1, TPFIN1 TPFIP2, TPFIN2 TPFIP3, TPFIN3 TPFIP4, TPFIN4 TPFIP5, TPFIN5 Type1 Signal Description Twisted-Pair/Fiber Outputs, Positive & Negative - Ports 0-5. O During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFO pins produce differential PECL outputs for fiber transceivers. Twisted-Pair/Fiber Inputs, Positive & Negative - Ports 0-5. I During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential 100BASE-TX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFI pins receive differential PECL inputs from fiber transceivers. 1. Type Column Coding: I = Input, O = Output. Table 3. Pin# LXT9763 Miscellaneous Signal Descriptions Symbol Type1 Signal Description2 Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: 91 94 TxSLEW_0 TxSLEW_1 I TxSLEW_1 0 0 1 1 TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 2.5 ns 3.1 ns 3.7 ns 4.3 ns 93 RESET I Reset. This active Low input is OR'ed with the control register Reset bit (0.15). When held Low, output pins go to inactive state. 1. Type Column Coding: I = Input, O = Output, A = Analog. 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet 13 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 3. Pin# LXT9763 Miscellaneous Signal Descriptions (Continued) Symbol Type1 Signal Description2 Address <4:0>. Sets base address. Each port adds its port number to this address to determine its PHY address. Port 0 Address = Base + 0. Port 1 Address = Base + 1. Port 2 Address = Base + 2. Port 3 Address = Base + 3. Port 4 Address = Base + 4. Port 5 Address = Base + 5. Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k, 1% resistor. Reference Clock. A 25 MHz clock is required at this pin. No Connection. These pins should be left floating. 101 100 99 98 97 ADD_4 ADD_3 ADD_2 ADD_1 ADD_0 I I I I I 102 92 127-134 RBIAS REFCLK N/C I I - 1. Type Column Coding: I = Input, O = Output, A = Analog. 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Table 4. LXT9763 Power Supply Signal Descriptions Pin# Symbol VCCT VCCR VCCD Type Signal Description Transmitter Supply. +3.3V supply for analog circuits. Receiver Supply. +3.3V supply for analog circuits. Digital Power Supply - Core. +3.3V supply for core digital circuits. Digital Power Supply - I/O Ring. 3.3V supply for digital I/O circuits. Regardless of the IO supply, digital I/O pins remain tolerant of 5V signal levels. Digital Ground. Ground return for both core and I/O digital supplies (VCCD and VCCIO). Analog Ground. Ground return for analog supply. Substrate Ground. Ground for chip substrate. 107, 114, 123, 138, 147, 154 106, 115, 122, 139, 146, 155 80, 89, 179 15, 31, 52, 67, 193, 208 1, 16, 32, 53, 68, 81, 87, 88, 178, 192 103, 110, 111, 118, 119, 126, 135, 142, 143, 150, 151, 158 78 VCCIO - GNDD GNDA GNDS - Table 5. Pin# 163 164 165 166 167 TDI TDO TMS TCK TRST LXT9763 JTAG Test Signal Descriptions Type1 I / IP O I / IP I / ID I / IP Signal Description Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock for JTAG test (REFCLK). Test Reset. Reset input for JTAG test. Symbol 1. Type Column Coding: I = Input, O = Output, A = Analog, IP = weak internal pull-up, ID = weak internal pull-down. 14 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 6. Pin# 181 182 183 LXT9763 LED Signal Descriptions Type1 Signal Description Port 0 LED Drivers 1 -3. These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 0 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Port 1 LED Drivers 1 -3. These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 1 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Port 2 LED Drivers 1 -3. These pins drive LED indicators for Port 2 Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 2 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Port 3 LED Drivers 1 -3. These pins drive LED indicators for Port 3. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 3 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Port 4 LED Drivers 1 -3. These pins drive LED indicators for Port 4. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 4 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Port 5 LED Drivers 1 -3. These pins drive LED indicators for Port 5. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 71 for details). Port 5 Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 7 on page 23 for details). Symbol LED/CFG0_1 LED/CFG0_2 LED/CFG0_3 I/OD/OS 176 177 180 LED/CFG1_1 LED/CFG1_2 LED/CFG1_3 I/OD/OS 173 174 175 LED/CFG2_1 LED/CFG2_2 LED/CFG2_3 I/OD/OS 170 171 172 LED/CFG3_1 LED/CFG3_2 LED/CFG3_3 I/OD/OS 162 168 169 LED/CFG4_1 LED/CFG4_2 LED/CFG4_3 I/OD/OS 159 160 161 LED/CFG5_1 LED/CFG5_2 LED/CFG5_3 I/OD/OS 1. Type Column Coding: I = Input, O = Output, OD = Open Drain, OS = Open Source. Datasheet 15 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.0 1.1 Functional Description Introduction The LXT9763 six-port Fast Ethernet 10/100 Transceiver supports 10 Mbps and 100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. Each port directly drives either a 100BASE-TX line (up to 100 meters) or a 10BASE-T line (up to 185 meters). The LXT9763 also supports 100BASE-FX operation via a Pseudo-ECL (PECL) interface. 1.1.1 OSPTM Architecture Intel's LXT9763 incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by high-speed DSP engines. This logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT9763 provides improved data recovery, EMI performance, and power consumption. 1.1.2 Comprehensive Functionality The LXT9763 provides six standard Media Independent Interfaces (MIIs) for 10/100 MACs, each serving an individual network port. The LXT9763 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT9763 reads its configuration pins to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT9763 auto-negotiates with it using Fast Link Pulse (FLP) bursts. If the PHY partner does not support auto-negotiation, the LXT9763 automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. The LXT9763 provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. 16 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 1.2 Interface Descriptions Figure 3. LXT9763 Interfaces MII Data I/F TX_CLKn TXDn_<3:0> TX_ENn TX_ERn RX_CLKn RXDn_<3:0> RX_DVn RX_ERn COLn CRSn MDIO TPFOPn TPFONn TPFIPn TPFINn Network I/F MII Mgmt I/F MDC MDINT ADD<4:0> Hardware Control I/F & Port LEDs LED/CFGn_1 LED/CFGn_2 LED/CFGn_3 RBIAS 22.1k VCCIO VCCD GNDD +3.3V +3.3V .01uF 1.2.1 10/100 Network Interface The LXT9763 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). Each of the six network interface ports consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. Refer to Table 2 on page 13 for specific pin assignments. The LXT9763 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output. When not transmitting data, the LXT9763 generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. 1.2.2 Twisted-Pair Interface When operating at 100 Mbps, the LXT9763 continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT9763 generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. The LXT9763 supports either 100BASE-TX or 10BASE-T connections over 100, Category 5, Unshielded Twisted Pair (UTP) cable. Only a transformer, RJ-45 connector, series capacitors and load resistor, and bypass capacitors are required to complete this interface. On the receive side, the Datasheet 17 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII internal impedance is high enough that it has no practical effect on the external termination circuit. On the transmit side, Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 3 on page 13) allow the designer to match the output waveform to the magnetic characteristics. 1.2.3 Fiber Interface The LXT9763 provides a PECL interface that complies with the ANSI X3.166 specification. This interface is suitable for driving a fiber-optic coupler. Fiber ports cannot be enabled via autonegotiation; they must be enabled via the MDIO interface. 1.2.4 Configuration Management Interface The LXT9763 provides both an MDIO interface and a hardware control interface (via the LED/ CFG pins) for device configuration and management. 1.2.5 MDIO Management Interface The LXT9763 supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT9763. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. The LXT9763 also supports additional registers for expanded functionality. The LXT9763 supports 12 internal registers per port (48 total), each of which is 16 bits wide. Specific register bits are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). The timing for the MDIO Interface is shown in Table 33 on page 57. MDIO read and write cycles are shown in Figure 5 (read) and Figure 6 (write). 1.3 MII Addressing The protocol allows one controller to communicate with multiple LXT9763 chips. Pins ADD_<4:0> determine the base address. Each port adds its port number to the base address to obtain its port address as shown in Figure 4. 18 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 4. Port Address Scheme BASE ADDR (ex. ADDR=4) LXT9763 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 PHY ADDR (BASE+0) ex. 4 PHY ADDR (BASE+1) ex. 5 PHY ADDR (BASE+2) ex. 6 PHY ADDR (BASE+3) ex. 7 PHY ADDR (BASE+4) ex. 8 PHY ADDR (BASE+5) ex. 9 1.3.0.1 MII Interrupts The LXT9763 provides a single interrupt pin available to all ports. Interrupt logic is shown in Figure 7. The LXT9763 also provides two dedicated interrupt registers for each port. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT9763. However, because it is a shared interrupt, it does not indicate which port is requesting service. Interrupts may be caused by one of four conditions: * * * * . Auto-negotiation complete Speed status change Duplex status change Link status change Figure 5. Management Interface Read Frame Structure MDC MDIO (Read) High Z 32 "1"s Preamble 0 ST 1 1 0 Op Code A4 A3 PHY Address A0 R4 R3 R0 Z 0 D15 D15D14 D14 D1 Data Read D1 D0 Idle Register Address Turn Around Write Datasheet 19 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 6. Management Interface Write Frame Structure MDC MDIO (Write) Idle 32 "1"s Preamble 0 ST 1 0 1 Op Code A4 A3 PHY Address A0 R4 R3 R0 1 0 Turn Around D15 D14 Data D1 D0 Idle Register Address Write Figure 7. Interrupt Logic Event X Enable Reg AND Event X Status Reg Per Event Force Interrupt Interrupt Enable . . . OR AND Per port . . . Port Combine Logic Interrupt Pin 1. Interrupt (Event) Status Register is cleared on read. 2. X = Any Interrupt capability 1.3.1 Hardware Control Interface The LXT9763 provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface consists of three Configuration (CFG) pins for each port. The CFG pins double as LED drivers. Refer to "Hardware Configuration Settings" on page 23 for additional details. 1.3.2 MII Data Interface The LXT9763 supports six standard MIIs (one per port). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT9763 and one or more Media Access Controllers (MACs). Separate parallel buses are provided for transmit and receive. This interface operates at either 2.5 MHz or 25 MHz. The speed is set automatically, once the operating conditions of the network link have been determined. 1.4 1.4.1 Operating Requirements Power Requirements The LXT9763 requires four power supply inputs, VCCD, VCCR, VCCT, and VCCIO. The digital and analog circuits require 3.3 V supplies (VCCD, VCCR and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground. 20 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 An additional supply may be used for the MII (VCCIO). VCCIO should be supplied from the same power source used to supply the controller on the other side of the MII interface. Refer to Table 17 on page 45 for MII I/O characteristics. As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in 17 on page 41. 1.5 1.5.1 Clock Requirements Reference Clock The LXT9763 requires a constant 25 MHz reference clock (REFCLK). The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e, PLL-based) to minmize transmit jitter. Refer to Table 18 on page 45 for clock timing requirements. 1.5.1.1 MII Clocks The LXT9763 requires an MDC reference clock for the MDIO serial channel. Typically operated at 2.5 MHz, the LXT9763 accepts MDC clocks as high as 8 MHz. Refer to Test Specifications, Table 18 on page 45, for MDC clock requirements. The LXT9763 supplies both MII data clocks (RX_CLK and TX_CLK) for each port. The MII data clocks run at 25 MHz for 100BASE-X operation and at 2.5 MHz for 10BASE-T operation. 1.6 Initialization When the LXT9763 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 8. The LXT9763 can be initialized to allow auto-negotiation/ parallel-detection to establish a link, or it may be forced to any of the following configurations: * * * * * 100FX (Fiber). 100TX, Full-Duplex 100TX, Half-Duplex 10BASE-T, Full-Duplex 10BASE-T, Half-Duplex When the network link is forced to a specific configuration, the LXT9763 immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT9763 begins the auto-negotiation / parallel-detection operation. Datasheet 21 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.6.1 Power-Down Mode The LXT9763 provides a per-port Power-Down Mode. Individual port power-down control is provided by bit 0.11 in the respective port Control Registers (refer to Table 38 on page 62). During individual port power-down, the following conditions are true: * The individual port is shut down. * The MDIO registers remain accessible. * The MDIO registers are unaffected. 1.6.2 Reset The LXT9763 provides both hardware and software resets. Configuration control of AutoNegotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to Table 7 on page 23 for pin settings and Table 38 on page 62 for register bit definitions). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset will not be detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0). Figure 8. Initialization Sequence Power-up or Reset Read H/W Control Interface Initialize MDIO Registers Pass Control to MDIO No Reset ? Yes 22 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 1.7 Hardware Configuration Settings The LXT9763 provides a hardware option to set the initial device configuration. The hardware option uses the three LED/CFG pins for each port. This provides three control bits per port, as listed in Table 7. The LED drivers can operate as either open drain or open source circuits as shown in Figure 9. The LED pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10 mA max current rating) as required by the hardware configuration. In applications where all ports are configured the same, several pins may be tied together with a single resistor. Note: Fiber operation cannot be selected via hardware. Fiber operation must be enabled via the MDIO port. . Figure 9. Hardware Configuration Settings VCC Configuration Bit = 1 LED/CFG Pin LED/CFG Pin Configuration Bit = 0 1. LEDs will automatically correct their polarity upon power-up or Table 7. Hardware Configuration Settings Pin Settings LED/CFGn_1 Resulting Register Bit Values Control Register 3 0 0 Full 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 Half 100 Full Half 100 1 0 1 1 Half 10/100 Full 1 1 1 1 0 1 0 0 0 1 1 0 1 0 0 Full 1 1 0 1 0 0 1 AutoNeg 0.12 Speed 0.13 FD 0.8 0 XXXX2 Auto-Negotiation Advertisement AN Advertisement Register 100FD 4.8 100TX 4.7 10 FD 4.6 10T 4.5 Desired Configuration AutoNeg Mode Speed Mode Duplex Mode Half 1 0 2 0 10 Disabled Enabled3 1. These pins set the default values for registers 0 and 4 accordingly. 2. X = Don't Care. 3. Do not select Fiber mode with Auto-Negotiation enabled. Datasheet 23 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.8 Establishing Link See Figure 10 for an overview of link establishment. 1.8.1 Auto-Negotiation The LXT9763 attempts to auto-negotiate with its counter-part across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "page". All devices that support auto-negotiation must implement the "Base Page" defined by IEEE 802.3 (registers 4 and 5). LXT9763 also supports the optional `Next Page' function (registers 7 and 8). 1.8.1.1 Base Page Exchange By exchanging Base Pages, the LXT9763 and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds the highest common capabilities that both sides support. Both sides then exchange more pages, and finally agree on the operating state of the line. 1.8.1.2 Next Page Exchange Additional information, above that required by base page exchange is also sent via "Next Pages'. The LXT9763 fully supports the 802.3 method of negotiation via Next Page exchange. 1.8.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: * After power-up, power-down, or reset, the power-down recovery time, (see Table 34 on page 57), must be exhausted before proceeding. * Set the auto-negotiation advertisement bits. * Enable auto-negotiation (set MDIO bit 0.12 = 1). Note: Do not enable Auto-Negotiation if fiber mode is selected. 1.8.1.4 Parallel Detection In parallel with auto-negotiation, the LXT9763 also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT9763 to communicate with devices that do not support auto-negotiation. 24 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 10. Overview of Link Establishment Power-Up, Reset, Link Failure Start Disable Auto-Negotiation 0.12 = 0 Check Value 0.12 0.12 = 1 Enable Auto-Neg/Parallel Detection Go To Forced Settings Attempt AutoNegotiation Listen for 100TX Idle Symbols Listen for 10T Link Pulses Done YES Link Set NO 1.9 MII Operation Figure 11 is a simple block diagram of the MII data interface. Separate channels are provided for transmitting data from the MAC to the LXT9763 (TXD), and for passing data received from the line to the MAC (RXD). Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL and CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER. The LXT9763 supplies both transmit and receive clock signals as well as separate outputs for carrier sense and collision. Data is normally exchanged across the MII in 4-bit-wide nibbles. However, two alternative data exchange methods are provided. A 5-bit symbol mode is available via bit 16.11 for 100M operation. Refer to Table 47 on page 68 for additional information on these bit settings. Datasheet 25 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 11. MII Data Interface TX_CLKn TX_ENn TXD<3:0>n TX_ERn Media Access Controller (MAC) RX_CLKn RX_DVn RXD<3:0>n RX_ERn CRSn COLn Orca_6M 1.9.1 Transmit Clock The LXT9763 is the master clock source for data transmission. It automatically sets the speed of TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK will be set to 25 MHz. If the port is operating at 10 Mbps, TX_CLK will be set to 2.5 MHz. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT9763 samples these signals on the rising edge of TX_CLK. 1.9.2 Transmit Enable The MAC must assert TX_EN synchronously with the first nibble of preamble, and de-assert TX_EN after the last bit of the packet. 1.9.3 Receive Data Valid The LXT9763 asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed: * For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet. * For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. 1.9.4 Error Signals Whenever the LXT9763 receives an errored symbol from the network, it asserts RX_ER and drives "1110" on the RXD pins. RX_ER is synchronous with RX_CLK. When the MAC asserts TX_ER, the LXT9763 will drive "H" symbols out on the line. TX_ER must be synchronous with TX_CLK. 26 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 1.9.5 Carrier Sense Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received from the network and in some modes when a packet is transmitted. On transmit, CRS is asserted on a 10 Mbps or 100 Mbps half-duplex link. Carrier sense is not generated on transmit when the link is operating in full-duplex mode. 1.9.6 Collision The LXT9763 asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 8 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. 1.9.7 Loopback The LXT9763 provides two loopback functions, operational and test (see Table 8). 1.9.7.1 Operational Loopback Operational loopback is provided for 10 Mbps half-duplex links when bit 16.8 = 0. Data transmitted by the MAC (TXData) will be looped back on the receive side of the MII (RXData). Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1. 1.9.7.2 Test Loopback A test loopback function is provided for diagnostic testing of the LXT9763. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT9763 and returned to the MAC. Test loopback is available for 100TX, 100FX, and 10T operation. Test loopback is enabled by setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). Loopback paths are shown in Figure 12. Figure 12. Loopback Paths LXT9763 FX Driver MII 10T Loopback Digital Block 100X Loopback Analog Block TX Driver Datasheet 27 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 8. Speed Carrier Sense, Loopback, and Collision Conditions Duplex Condition Full-Duplex Carrier Sense Receive Only Transmit or Receive Receive Only Transmit or Receive Transmit or Receive Test1 Loopback Yes No Yes No None Operational Loopback No No No Yes No Collision None Transmit and Receive None Transmit and Receive Transmit and Receive 100 Mbps Half-Duplex Full-Duplex 10 Mbps Half-Duplex, 16.8 = 0 Half-Duplex, 16.8 = 1 1. Test Loopback is enabled when 0.14 = 1 1.10 1.10.1 100 Mbps Operation 100BASE-X Network Operations During 100BASE-X operation, the LXT9763 transmits and receives 5-bit symbols across the network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT9763 sends out Idle symbols on the line. As shown in Figure 13, the MAC starts each transmission with a preamble pattern. As soon as the LXT9763 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT9763 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to transmitting Idle symbols. In 100TX mode, the LXT9763 scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are descrambled and decoded and sent across the MII to the MAC. Figure 14 shows the internal signal flow between the MII and the network interface. In 100FX mode, the LXT9763 transmits and receives NRZI signals across the PECL interface. An external 100FX transceiver module is required to complete the fiber connection. Figure 13. 100BASE-X Frame Format 64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (4 Octets) (Pad to minimum packet size) (> 12 Octets) P0 P1 P6 SFD DA DA SA SA L1 L2 D0 D1 Dn CRC I0 IFG Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD) Start-of-Frame Delimiter (SFD) Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD) 28 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 14. 100BASE-TX Data Path Standard Data Flow D0 D1 D2 D3 Parallel to Serial +1 0 0 -1 0 Scramble D0 D1 D2 D3 Serial to Parallel 4B/5B S0 S1 S2 S3 S4 DeScramble MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... Symbol (5B) Mode Data Flow S0 S1 S2 S3 S4 Scrambler Bypass Data Flow S0 S1 S2 S3 S4 Serial to Parallel Parallel to Serial +1 0 0 -1 0 Parallel to Serial +1 Scramble 0 0 -1 0 S0 Serial to Parallel S1 S2 S3 S4 DeScramble MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... D0 D1 D2 D3 4B/5B S0 S1 S2 S3 S4 MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... 1.10.2 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT9763 is a Physical Layer 1 (PHY) device. The LXT9763 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss LXT9763 operation from the reference model point of view. 1.10.2.1 PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. (For symbol mode operation, the 4B/5B function can be bypassed by setting 16.11 = 1.) For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. Datasheet 29 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data, following Table 9 on page 30, until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. Dribble Bits The LXT9763 handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble is passed across the MII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble is not sent onto the MII bus Figure 15. Protocol Sublayers MII Interface PCS Sublayer LXT9763 Encoder/Decoder Serializer/De-serializer PMA Sublayer Link/Carrier Detect PECL Interface PMD Sublayer Scrambler/ De-scrambler Fiber Transceiver 100BASE-TX . 100BASE-FX Table 9. Code Type 4B/5B Coding 4B Code 3210 0000 0001 0010 0011 Name 0 1 2 3 5B Code 43210 11110 01001 10100 10101 Data 0 Data 1 Data 2 Data 3 Interpretation 1. 2. 3. 4. The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. 30 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 9. Code Type 4B/5B Coding (Continued) 4B Code 3210 0100 0101 0110 Name 4 5 6 7 8 9 A B C D E F I 1 5B Code 43210 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 1 1 1 11 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Data D Data E Data F Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Interpretation DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 Data B Data C IDLE undefined 0101 Idle. Used as inter-stream fill code Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2 Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid J2 K2 T R 3 3 CONTROL 0101 undefined undefined undefined undefined undefined undefined H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid INVALID undefined undefined undefined undefined undefined undefined undefined 1. 2. 3. 4. The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. Datasheet 31 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.10.2.2 PMA Sublayer Link In 100TX and FX modes, the LXT9763 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link will be taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. The LXT9763 reports link failure via the MII status bits (1.2, 17.10, and 19.4) and interrupt functions. If auto-negotiate is enabled, link failure causes the LXT9763 to re-negotiate. Link Failure Override The LXT9763 normally transmits 100 Mbps data packets or Idle symbols only if the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this function, allowing the LXT9763 to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT9763 automatically begins transmitting FLP bursts if the link goes down. Carrier Sense For 100TX and 100FX links, a Start-of-Stream Delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without / T/R; however, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons: * De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to appear somewhat shorter to the MAC than it actually is on the wire. * CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in halfduplex mode. Receive Data Valid The LXT9763 asserts RX_DV to indicate that the received data maps to valid symbols. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller. 1.10.2.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/Descrambler (100TX Only) The scrambler spreads the signal power spectrum and further reduces EMI using an 11-bit, nondata-dependent polynomial. The receiver automatically decodes the polynomial whenever it receives IDLE symbols. 32 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scramber bypass is provided for diagnostic and test support. Baseline Wander Correction (100TX Only) The LXT9763 provides a baseline wander correction function, making the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT9763 baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths. Polarity Correction The LXT9763 automatically detects and corrects for the condition where the receive signal (TPIP/ N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-offrame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. 1.10.2.4 Fiber PMD Sublayer The LXT9763 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT9763 uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications. Far End Fault Indications The LXT9763 does not provide Signal Detect pins and therefore does not independently detect signal faults. However, the device can detect a far end fault code embedded in the received data stream and uses bit 1.4 to report far end fault indications received from its link partner. Bit 1.4 is set once and clears when read. A far end fault condition causes the LXT9763 to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. 1.11 10 Mbps Operation The LXT9763 can operate as a standard 10BASE-T transceiver, supporting all the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9763 transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT9763 drives link pulses onto the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT9763 and sent across the MII to the MAC. The 10M reversed polarity correction function is the same as the 100M function described on page 33. Datasheet 33 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII The LXT9763 does not support fiber connections at 10 Mbps. 1.11.1 10T Preamble Handling The LXT9763 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when 16.5 = 0, the LXT9763 strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT9763 are the SFD "5D" hex followed by the body of the packet. In 10T mode with 16.5 = 1, the LXT9763 passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10T loopback, the LXT9763 loops back whatever the MAC transmits to it, including the preamble. 1.11.2 10T Carrier Sense For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. Refer to Table 47 on page 68. 1.11.3 10T Dribble Bits The LXT9763 device handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble is sent across the MII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble is not sent onto the MII bus. 1.11.4 10T Link Test In 10T mode, the LXT9763 always transmit link pulses. If the Link Test function is enabled, it monitors the connection for link pulses. Once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission will be disabled. If the Link Test function is disabled (Force Link Pass), the LXT9763 will transmit to the connection regardless of detected link pulses. The Link Test function can be disabled by setting bit 16.14 = 1. 1.11.4.1 Link Test Failure Link Test failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT9763 returns to the auto-negotiation phase if auto-negotiation is enabled. 10T Jabber If a transmission exceeds the jabber timer, the LXT9763 will disable the transmit and loopback functions. See 29 on page 55 for jabber timing parameters. The LXT9763 automatically exits jabber mode after the unjab time has expired. This function can be disabled by setting bit 16.10 = 1. 34 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 1.12 1.12.1 Monitoring Operations Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: * Bit 17.7 is set to 1 once the auto-negotiation process is completed. * Bits 1.2 and 17.10 are set to 1 once the link is established. * Additional bits in Register 1 (refer to Table 39 on page 62) and Register 17 (refer to Table 48 on page 68) can be used to determine the link operating conditions and status. 1.12.1.1 Monitoring Next Page Exchange The LXT9763 offers an Alternate Next Page mode to simplify the next page exchange process. Normally, bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled (16.1 = 1), bit 6.1 is automatically cleared whenever a new negotiation process takes place. This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT9763 uses bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Bits 6.1 and 6.5 are cleared when read. 1.12.2 Per-Port LED Driver Functions The LXT9763 incorporates three direct drive LEDs per port. On power up all the LEDs will light for approximately 1 second after reset de-asserts. Each LED can be programmed to one of several different display modes using the LED Configuration Register. Each per-port LED can be programmed (refer to Table 51 on page 71) to indicate one the following conditions: * * * * * * Operating Speed Transmit Activity Receive Activity Collision Condition Link Status Duplex Mode The LEDs can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications: * If Link is down LED is off. * If Link is up LED is on. * If Link is up AND activity is detected, the LED will blink at the stretch interval selected by bits 20.3:2 and will continue to blink as long as activity is present. The LED driver pins are also used to provide initial configuration settings. The LED pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10mA max current rating) as required by the hardware configuration. Refer to the discussion of "Hardware Configuration Settings" on page 23 for details. Datasheet 35 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 1.12.2.1 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, the pulse stretch time will be further extended. When an event such as receiving a packet occurs it will be edge detected and it will start the stretch timer. The LED driver will remain asserted until the stretch timer expires. If another event occurs before the stretch timer expires then the stretch timer will be reset and the stretch time will be extended. When a long event (such as duplex status) occurs it will be edge detected and it will start the stretch timer. When the stretch timer expires the edge detector will be reset so that a long event will cause another pulse to be generated from the edge detector which will reset the stretch timer and cause the LED driver to remain asserted. Figure 16 shows how the stretch operation functions. Figure 16. LED Pulse Stretching Event LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active Low. 1.13 Boundary Scan (JTAG1149.1) Functions LXT9763 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. 1.13.1 Boundary Scan Interface This interface consists of five pins (TMS,TDI,TDO,TCK and TRST). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is internally pulled down. TDO does not have an internal pull-up or pull-down. 1.13.2 State Machine The TAP controller is a 16 Bit state machine driven by the TCK and TMS pins. Upon reset the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is High for five TCK periods. 1.13.3 Instruction Register After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in Table 11. 36 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 1.13.4 Boundary Scan Register Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 10. Table 10. BSR Mode of Operation Mode 1 2 3 4 Description Capture Shift Update System Function Table 11. Supported JTAG Instructions Name EXTEST IDCODE SAMPLE High Z Clamp BYPASS Code 0000000000000000 1111111111111110 1111111111111110 1111111111001111 1111111111101111 1111111111111111 External Test ID Code Inspection Sample Boundary Force Float Clamp Bypass Scan Description BSR ID REG BSR Bypass BSR Bypass Mode Data Register EXTEST IDCODE SAMPLE High Z Clamp BYPASS Table 12. Device ID Register 31:28 Version 0000 27:12 Part ID (hex) 2623 11:8 Jedec Continuation Characters 0000 7:1 JEDEC ID1 111 1110 0 Reserved 1 1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110) which becomes 111 1110. Datasheet 37 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 2.0 2.1 Application Information Design Recommendations The LXT9763 is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. To achieve maximum performance from the LXT9763, attention to detail and good design practices are required. Refer to the LXT9763 Design and Layout Guide for detailed design and layout information. 2.1.1 General Design Guidelines Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: * Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. * Use ample bulk and decoupling capacitors throughout the design (a value of .01 F is recommended for decoupling caps). * * * * * * Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. Do not route any digital signals between the LXT9763 and the RJ-45 connectors at the edge of the board. edge of the board. Use this area for chassis ground, or leave it void. * Do not extend any circuit power and ground plane past the center of the magnetics or to the 2.1.2 Power Supply Filtering Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and degrade line performance. The best approach is to minimize ground noise as much as possible using good general techniques and by filtering the VCC plane. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems: * Poorly-regulated or over-burdened power supplies * Wide data busses (32-bits+) running at a high clock rate * DC-to-DC converters 38 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Intel recommends filtering the power supply to the analog VCC pins of the LXT9763. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9763, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT9763. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one LXT9763, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. Beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 F) should be place on each side of each bead. In addition, a high-frequency bypass cap (.01 F) should be placed near each analog VCC pin. 2.1.3 Power and Ground Plane Layout Considerations Great care needs to be taken when laying out the power and ground planes. * Follow the guidelines in the LXT9761/62/63/81/82 Design & Layout Guide for locating the split between the digital and analog VCC planes. * Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, away from the magnetics, and away from the RJ45 connectors. * Place the layers so that the TPFOP/N and TPFIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N. 2.1.3.1 Chassis Ground For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2 kV isolation to the Bob Smith termination. 2.1.4 MII Terminations The LXT9763 MII has high output impedance (250 - 350) and normally only requires termination on the output signals in designs with long traces (>3 inches). Use series termination resistors on all RX_CLK and TX_CLK signals to minimize reflections. Place the resistor as close to the device as possible. Use a software trace termination package to select an optimal resistance value for the specific trace. If this is not possible, use a 50 resistor value. Datasheet 39 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 2.1.5 The RBIAS Pin The LXT9763 requires a 22.1 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. Surround the RBIAS trace with a filtered ground; do not run high-speed signals next to RBIAS. 2.1.6 The Twisted-Pair Interface Follow standard guidelines for a twisted-pair interface: * * * * * Place the magnetics as close as possible to the LXT9763. Keep transmit pair traces as short as possible; both traces should have the same length. Avoid vias and layer changes as much as possible. Keep the transmit and receive pairs apart to avoid cross-talk. Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. to supply center tap current to all ports. All six ports draw a combined total of 370 mA so the bead should be rated at 560 mA. * Improve EMI performance by filtering the TPO center tap. A single ferrite bead may be used 2.1.6.1 Magnetics Information The LXT9763 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 1.5 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 13 for transformer requirements. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. 2.1.7 The Fiber Interface The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic transceiver. The LXT9763 does not provide Signal Detect pins and therefore does not receive or transmit fault signals. The transmit and receive pair should be DC-coupled to the transceiver, and biased appropriately. Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 19 on page 43 shows a typical example. Table 13. Magnetics Requirements Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - 40 Nom 1:1 1:1 0.6 - 1.5 - Max - - 1.1 - - - Units - - dB Test Condition H kV dB .1 to 60 MHz 40 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 13. Magnetics Requirements Parameter Min 35 -16 Return Loss -10 Rise Time 2.0 - - - 3.5 dB ns 80 MHz 10% to 90% Nom - - Max - - Units dB dB Test Condition 60 to 100 MHz 30 MHz 2.2 Typical Application Circuits Figure 18 shows a typical layout of the LXT9763 twisted-pair interface in a dual-high (stacked) RJ-45 application. Figure 17. Power and Ground Supply Connections LXT9763 GNDS RBIAS GNDA .01F .01F 22.1 k 1% VCCT VCCR Analog Supply Plane Ferrite Bead 10F + Digital Supply Plane + 10F VCCD .01F +3.3V GNDD 10F .01F VCCIO + +3.3V Datasheet 41 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 18. Typical Twisted-Pair Interface A TPFOP 1:1 1 RJ45 1 2 3 TPFON TPFIP 270 pF 5% 1:1 50 1% 50 50 4 50 5 6 LXT9763 TPFIN 2 50 1% 50 50 7 50 8 270 pF 5% 0.01 F 3 * * * = 0.001 F / 2.0 kV 4 VCCT 0.1F .01F GNDA 5 1. The 100 transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive pair center-tap do not require a 2 kV termination. 3. Center tap current may be supplied from 3.3V VCCA as shown. However, additional power savings may be realized by supplying the center-tap from from a 2.5V current source. In either case a single ferrite bead (rated at 560 mA) may be used to supply center tap current to all ports. 4. Receive common mode bypass cap may improve BER performance in systems with noisy power supplies. 5. Recommended 0.1F capacitor to improve the EMI performance. 42 Datasheet To Twisted-Pair Network Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 19. Typical Fiber Interface VCCD +3.3V 16 50 50 0.1 mF GNDD TPFONn TPFOPn TDTD+ To Fiber Network LXT9763 Fiber Txcvr SD VCCD +3.3V 130 130 0.1 mF GNDD 1 TPFINn TPFIPn 82 82 GNDD RDRD+ 1. Refer to fiber transceiver manufacturer's recommendations for termination circuitry. Example shown above is suitable for HFBR5900-series devices. Datasheet 43 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII 3.0 Note: Test Specifications Table 14 through Table 34 and Figure 20 through Figure 34 represent the performance specifications of the LXT9763. These specifications are guaranteed by test except where noted "by design." Minimum and maximum values listed in Table 16 through Table 34 apply over the recommended operating conditions specified in Table 15. Table 14. Absolute Maximum Ratings Parameter Supply voltage Operating temperature Ambient Case Storage temperature Sym VCC TOPA TOPC TST Min -0.3 0 - -65 Max 4.0 +70 +120 +150 Units V C C C Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Operating Conditions Parameter Ambient Recommended operating temperature Case Recommended supply voltage2 VCC current Analog & Digital I/O 100BASE-TX 100BASE-FX 10BASE-T Auto-Negotiation TOPC Vcca, Vccd Vccio ICC ICC ICC ICC 0 3.15 3.15 - - - - - 3.3 3.3 1153- - 115 - 114.5 3 3 Sym TOPA Min 0 Typ1 - Max 70 110 3.45 3.45 1303 - 130 130 3 3 Units C C V V mA mA mA mA 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 3. Per port @ 3.3V. Table 16. Digital I/O Characteristics 1 Parameter Input Low voltage3 Input High voltage3 Input current Output Low voltage Output High voltage Sym VIL VIH II VOL VOH Min - 2.0 -10 - 2.4 Typ2 - - - - - Max 0.8 - 10 0.4 - Units V V Test Conditions - - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA A V V 1. Applies to all pins except MII pins. Refer to Table 17 for MII I/O Characteristics. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 3. Does not apply to REFCLK. Refer to Table 18 for clock input levels. 44 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 17. Digital I/O Characteristics - MII Pins Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage VOH Driver output resistance (Line driver output enabled) RO RO 2 2 Sym VIL VIH II VOL VOH Min - 2.0 -10 - 2.2 2.0 - - Typ1 - - - - - - 100 100 Max 0.8 - 10 0.4 - - - - Units V V - - Test Conditions A V V V 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA, VCC = 3.3V IOH = -4 mA, VCC = 2.5V VCC = 2.5V VCC = 3.3V 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. Table 18. Required Reference Clock (REFCLK) Characteristics Parameter Input Low voltage Input High voltage Input frequency Input clock frequency tolerance Input clock duty cycle 1 1 Sym VIL VIH F Min - 2.0 - - 40 Typ1 - - 25 - - Max 0.8 - - 100 60 Units V V MHz ppm % Test Conditions - - - - - f Tdc 1. Parameter is guaranteed by design; not subject to production testing. Table 19. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Sym VP Vss TRF TRFS - VO Min 0.95 98 3.0 - - - Typ1 - - - - - - Max 1.05 102 5.0 0.5 0.5 5 Units V % ns ns ns % Test Conditions Note 2 Note 2 Note 2 Note 2 Offset from 16ns pulse width at 50% of pulse peak - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Datasheet 45 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 20. 100BASE-FX Transceiver Characteristics Parameter Sym Min Typ1 Transmitter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) VOP TRF - 0.6 - - - - - Receiver Peak differential input voltage Common mode input range VIP VCMIR 0.55 - - - 1.5 VCC - 0.7 V V - - 1.5 1.9 1.4 V ns ns 10 <-> 90% - - 2.0 pF load Max Units Test Conditions 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 21. 10BASE-T Transceiver Characteristics Parameter Sym Min Typ1 Transmitter Peak differential output voltage Link transmit period Transmit timing jitter added by the MAU and PLS sections 3, 4 VOP - - 2.2 8 0 - - - Receiver Link min receive timer Link max receive timer Time link loss receive Differential squelch threshold 1. 2. 3. 4. 5. TLRmin TLRmax TLL VDS 2 50 50 - 4 64 64 - 7 150 150 - ms ms ms mV Peak - - - 5 MHz square wave input 2.8 24 11 V ms ns Note 2 - Note 5 Max Units Test Conditions Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Parameter is guaranteed by design; not subject to production testing. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. After line model specified by IEEE 802.3 for 10BASE-T MAU. 46 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 20. 100BASE-TX Receive Timing (4B Mode) 0ns 250ns TPFI t4 CRS t3 RX_DV t1 t2 RXD<3:0> RX_CLK t6 COL t7 t5 Table 22. 100BASE-TX Receive Timing Parameters (4B Mode) Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted Sym t1 Min 10 Typ1 - Max - Units ns Test Conditions - t2 t3 t4 t5 t6 t7 10 - - 13 - 13 - 4 10 14 14 18 - - - 24 20 24 ns BT BT BT BT BT - - - - - - 6. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 47 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 21. 100BASE-TX Transmit Timing (4B Mode) 0ns 250ns t1 TX_CLK TX_EN t2 TXD<3:0> t5 TPFO t3 CRS t4 Table 23. 100BASE-TX Transmit Timing Parameters (4B Mode) Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency) Sym t1 t2 t3 t4 t5 Min 15 0 - - - Typ1 - - 44 52 13 Max - - - - - Units ns ns ns ns BT Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 48 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 22. 100BASE-TX Receive Timing (5B Mode) 0ns 0ns 250ns 250ns TPFI TPFI t4 t4 CRS CRS t3 t3 RX_DV RX_DV t1 t1 t2 t2 RXD<4:0> RXD<4:0> RX_CLK RX_CLK t6 t6 COL COL Table 24. 100BASE-TX Receive Timing Parameters (5B Mode) Parameter RXD<4:0>, RX_DV, RX_ER setup to RX_CLK High RXD<4:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<4:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 Min 10 10 - - - - - Typ1 - - 4 14 19 14 19 Max - - - - - - - Units ns ns BT BT BT BT BT Test Conditions - - - - - - - t5 t5 t7 t7 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 49 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 23. 100BASE-TX Transmit Timing (5B Mode) 0ns 250ns t1 TX_CLK TX_EN t2 TXD<4:0> t5 TPFO t3 CRS t4 Table 25. 100BASE-TX Transmit Timing Parameters (5B Mode) Parameter TXD<4:0>, TX_EN, TX_ER setup to TX_CLK High TXD<4:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPOP out (Tx latency) Sym t1 t2 t3 t4 t5 Min 15 0 - - - Typ1 - - 44 52 6 Max - - - - - Units ns ns ns ns BT Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 50 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 24. 100BASE-FX Receive Timing 0ns 250ns TPFI t4 CRS t3 RX_DV t1 t2 RXD<3:0> RX_CLK t6 COL t7 t5 Table 26. 100BASE-FX Receive Timing Parameters Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 Min 10 10 - - - - - Typ1 - - 4 10 14 10 14 Max - - - - - - - Units ns ns BT BT BT BT BT Test Conditions - - - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 51 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 25. 100BASE-FX Transmit Timing 0ns 250ns t1 TXCLK TX_EN t2 TXD<3:0> t5 TPFO t3 CRS t4 Table 27. 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency) Sym t1 t2 t3 t4 t5 Min 15 0 - - - Typ1 - - 3 4 13 Max - - - - - Units ns ns BT BT BT Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 52 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 26. 10BASE-T Receive Timing RX_CLK t3 RXD, RX_DV, RX_ER t1 t2 t4 t5 CRS t6 TPFI t9 COL t8 t7 Table 28. 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER setup to RX_CLK High RXD, RX_DV, RX_ER hold from RX_CLK High TPFI in to RXD out (Rx latency) CRS asserted to RXD, RX_DV, RX_ER asserted RXD, RX_DV, RX_ER de-asserted to CRS de-asserted TPFI in to CRS asserted TPFI quiet to CRS de-asserted TPFI in to COL asserted TPFI quiet to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 t8 t9 Min 10 10 - - - - - - - Typ1 - - 6.6 18 1 2.5 12 3 12 Max - - - - - - - - - Units ns ns BT BT BT BT BT BT BT Test Conditions - - - - - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CRS is asserted. RXD/RX_DV are driven at the start of SFD (64 BT). Datasheet 53 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 27. 10BASE-T Transmit Timing TX_CLK t1 TXD, TX_EN, TX_ER t2 t3 t4 CRS t5 TPFO Table 29. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency) Sym t1 t2 t3 t4 t5 Min 10 0 - - - Typ1 - - 2 1 280 Max - - - - - Units ns ns BT BT ns Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 28. 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN t1 COL t2 54 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 30. 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) delay after TX_EN off COL (SQE) pulse duration Sym t1 t2 Min 0.65 0.5 Typ1 - - Max 1.6 1.5 Units Test Conditions - - s s 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 29. 10BASE-T Jab and Unjab Timing TX_EN t1 TXD t2 COL Table 31. 10BASE-T Jab and Unjab Timing Parameters Parameter Maximum transmit time Unjab time Sym t1 t2 Min 20 - Typ1 - - Max 150 750 Units ms ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 30. Auto Negotiation and Fast Link Pulse Timing Clock Pulse Data Pulse Clock Pulse TPFOP t1 t2 t3 t1 Datasheet 55 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 31. Fast Link Pulse Timing FLP Burst FLP Burst TPFOP t4 t5 Table 32. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst Sym t1 t2 t3 t4 t5 - Min - 55.5 111 - 8 17 Typ1 100 - - 2 - - Max - 69.5 139 - 24 33 Units ns Test Conditions - - - - - - s s ms ms ea 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 32. MDIO Write Timing (MDIO Sourced by MAC) MDC t1 t2 MDIO 56 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Figure 33. MDIO Read Timing (MDIO Sourced by PHY) MDC t3 MDIO Table 33. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY Sym t1 1 10 t2 1 10 t3 - 130 - ns MDC = 8 MHz - - - 300 ns ns MDC = 8 MHz MDC = 2.5 MHz - - - - ns ns MDC = 8 MHz MDC = 2.5 MHz Min 10 Typ1 - Max - Units ns Test Conditions MDC = 2.5 MHz 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 34. Power-Up Timing v1 VCC MDIO,etc t1 Table 34. Power-Up Timing Parameters Parameter Voltage threshold Power Up delay Sym v1 t1 Min - - Typ1 2.9 - Max - 500 Units V ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 57 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 35. RESET And Power-Down Recovery Timing RESET t1 t2 MDIO,etc Table 35. RESET and Power-Down Recovery Timing Parameters Parameter RESET pulse width RESET recovery delay Sym t1 t2 Min 10 - Typ1 - 1 Max - - Units ns ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 58 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 4.0 Register Definitions The LXT9763 register set includes multiple 16-bit registers. Refer to Table 36 for a complete register listing and to Table 37 for a complete bit map. Table 38 through Table 53 provide additional details. * Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation" sections of the IEEE 802.3 specification. * Additional registers (16 through 30) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions. Table 36. Register Set Address 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21-27 28 29 30 31 Control Register Status Register PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Received Next Page Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Extended Status Register Port Configuration Register Quick Status Register Interrupt Enable Register Interrupt Status Register LED Configuration Register Reserved Transmit Control Register #1 Reserved Transmit Control Register #2 Reserved Refer to Table 53 on page 72 Refer to Table 52 on page 72 Register Name Bit Assignments Refer to Table 38 on page 62 Refer to Table 39 on page 62 Refer to Table 40 on page 63 Refer to Table 41 on page 64 Refer to Table 42 on page 64 Refer to Table 43 on page 65 Refer to Table 44 on page 66 Refer to Table 45 on page 67 Refer to Table 46 on page 67 Not Implemented Not Implemented Not Implemented Refer to Table 47 on page 68 Refer to Table 48 on page 68 Refer to Table 49 on page 69 Refer to Table 50 on page 70 Refer to Table 51 on page 71 Datasheet 59 Table 37. Register Bit Map Bit Fields Reg Title B15 Control Register Control Reset Loopback Speed Select Isolate A/N Enable Power Down Re-start A/N Duplex Mode COL Test Speed Select B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved Status Register Status 100T4 100X Full Duplex 100X Half Duplex 10T Full Duplex 10T Half Duplex 100T2 Full Duplex 100T2 Half Duplex Extended Status Reserved PHY ID Registers MF Preamble Suppress A/N Complete Remote Fault A/N Ability Link Status Jabber Detect Extended Capability LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII PHY ID 1 PHY ID2 PHY ID No 15 14 13 12 11 10 9 8 7 6 MFR Model No Auto-Negotiation Advertisement Register 5 4 3 2 1 0 MFR Rev No A/N Advertise Next Page Reserved Reserved Remote Fault Asymm Pause Pause 100T4 100TX Full Duplex 100TX 10T Full Duplex 10T Auto-Negotiation Link Partner Base Page Ability Register IEEE Selector Field A/N Link Ability Next Page Ack Remote Fault Reserved Asymm Pause Pause 100T4 100TX Full Duplex 100TX 10T Full Duplex Auto-Negotiation Expansion Register 10T IEEE Selector Field A/N Expansion Reserved Link Page Partner Next Page Base Page Parallel Detect Next Page Able Received Fault Able Auto-Negotiation Next Page Transmit Register Link Partner A/N Able A/N Next Page Txmit Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field Auto-Negotiation Link Partner Next Page Ability Register A/N Next Page Rcv Next Page Ack Message Page Ack 2 Toggle Message / Unformatted Code Field Port Configuration Register 60 Datasheet Addr 0 1 2 3 4 5 6 7 8 Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Bit Fields Reg Title B15 Link Disable Quick Status Register Quick Status Reserved 10/100 Mode Link Auto-Neg Transmit Status Receiver Status Collision Status Duplex Mode Auto-Neg Complete Reserved Polarity Pause Error Txmit Disable Bypass Bypass 4B/ Jabber Scrambler 5B (10T) (100TX) (100TX) SQE (10T) CRS Select (10T) TP Loopback (10T) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Port Config Reserved FIFO Size PRE_EN Reserved Alternate Reserved Reserved Next Page Fiber Select PLL Lock Reserved Reserved Error Interrupt Enable Register Interrupt Enable Reserved Counter Mask Auto-Neg Speed Mask Mask Duplex Mask Link Mask Reserved Reserved Interrupt Enable Test Interrupt Interrupt Status Register Interrupt Status Reserved Counter Full Auto-Neg Done Speed Change LED Configuration Register LED Config LED1 LED2 Transmit Control Register #1 Analog #1 Line Length Reserved Transmit Control Register #2 Analog #2 Reserved Driver Amp Reserved LED3 Duplex Change Link Change Reserved MD Interrupt XTAL OK Reserved LED Freq Pulse Stretch Reserved/ Invalid Polarity Bandwidth Control Slew Control Datasheet 61 Table 37. Register Bit Map (Continued) Addr 16 17 18 19 20 28 30 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 38. Control Register (Address 0) Bit 0.15 0.14 Reset Loopback Name 1 = PHY reset. 0 = Normal operation. 1 = Enable loopback mode. 0 = Disable loopback mode. 0.6 0.13 Speed Selection 1 1 0 0 0.13 1 0 1 0 = Reserved. = 1000 Mbps (not allowed). = 100 Mbps. = 10 Mbps. R/W Note 2 00 Description Type 1 R/W SC R/W 0 0 Default 0.12 0.11 0.10 0.9 0.8 Auto-Negotiation Enable3 Power-Down Isolate Restart Auto-Negotiation Duplex Mode 1 = Enable Auto-Negotiation Process. 0 = Disable Auto-Negotiation Process. 1 = Power-down. 0 = Normal operation. 1 = Electrically isolate PHY from MII. 0 = Normal operation. 1 = Restart Auto-Negotiation Process. 0 = Normal operation. 1 = Full-Duplex. 0 = Half-Duplex. This bit is ignored by the LXT9763. 1 = Enable COL signal test. 0 = Disable COL signal test. 0.6 0.13 1 0 1 0 = Reserved. = 1000 Mbps (not allowed). = 100 Mbps. = 10 Mbps. 1 1 0 0 R/W R/W R/W R/W SC R/W Note 2 0 0 0 0 Note 2 0 0 0.7 Collision Test R/W 0.6 Speed Selection 1000 Mb/s R/W 00 0.5:0 Reserved Write as 0, ignore on Read R/W 00000 1. R/W = Read/Write. RO = Read Only. SC = Self Clearing when read. 2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to Table 7 on page 23). 3. Do not enable Auto-Negotiation if Fiber Mode is selected. Table 39. Status Register (Address 1) Bit 1.15 1.14 1.13 Name 100BASE-T4 100BASE-X FullDuplex 100BASE-X HalfDuplex Description 1 = PHY able to perform 100BASE-T4. 0 = PHY not able to perform 100BASE-T4. 1 = PHY able to perform full-duplex 100BASE-X. 0 = PHY not able to perform full-duplex 100BASE-X. 1 = PHY able to perform half-duplex 100BASE-X. 0 = PHY not able to perform half-duplex 100BASE-X. Type 1 RO RO RO Default 0 1 1 1. RO = Read Only. LL = Latching Low. LH = Latching High. 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. 62 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 39. Status Register (Address 1) (Continued) Bit 1.12 1.11 1.10 1.9 1.8 1.7 Name 10 Mbps Full-Duplex 10 Mbps Half-Duplex 100BASE-T2 FullDuplex 100BASE-T2 HalfDuplex Extended Status Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault2 Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Description 1 = PHY able to operate at 10 Mbps in full-duplex mode. 0 = PHY not able to operate at 10 Mbps full-duplex mode. 1 = PHY able to operate at 10 Mbps in half-duplex mode. 0 = PHY not able to operate at 10 Mbps in half-duplex. 1 = PHY able to perform full-duplex 100BASE-T2. 0 = PHY not able to perform full-duplex 100BASE-T2. 1 = PHY able to perform half duplex 100BASE-T2. 0 = PHY not able to perform half-duplex 100BASE-T2. 1 = Extended status information in register 15. 0 = No extended status information in register 15. 1 = ignore when read. 1 = PHY will accept management frames with preamble suppressed. 0 = PHY will not accept management frames with preamble suppressed. 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete. 1 = Remote fault condition detected. 0 = No remote fault condition detected. 1 = PHY is able to perform Auto-Negotiation. 0 = PHY is not able to perform Auto-Negotiation. 1 = Link is up. 0 = Link is down. 1 = Jabber condition detected. 0 = Jabber condition not detected. 1 = Extended register capabilities. 0 = Extended register capabilities. Type 1 RO RO RO RO RO RO Default 1 1 0 0 0 0 1.6 RO 0 1.5 1.4 1.3 1.2 1.1 1.0 RO RO/LH RO RO/LL RO/LH RO 0 0 1 0 0 1 1. RO = Read Only. LL = Latching Low. LH = Latching High. 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. Table 40. PHY Identification Register 1 (Address 2) Bit 2.15:0 Name PHY ID Number Description The PHY identifier composed of bits 3 through 18 of the OUI. Type 1 RO Default 0013 hex 1. RO = Read Only. Datasheet 63 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 41. PHY Identification Register 2 (Address 3) Bit 3.15:10 3.9:4 3.3:0 Name PHY ID number Manufacturer's model number Manufacturer's revision number Description The PHY identifier composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number. 4 bits containing manufacturer's revision number. Type 1 RO RO RO Default 011110 001001 XXXX 1. RO = Read Only. Figure 36. PHY Identifier Bit Mapping a b c r s x Organizationally Unique Identifier 1 2 3 0 0 1 3 9 3 18 19 24 I/G 15 0 15 10 4 0 PHY ID Register #1 (Address 2) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 PHY ID Register #2 (Address 3) 1 1 0 X X X X X X 0 0 0 0 0 0 0 2 B 7 5 0 3 0 00 20 7B The Level One OUI is 00207B hex. Manufacturer's Model Number Revision Number Table 42. Auto Negotiation Advertisement Register (Address 4) Bit 4.15 4.14 4.13 4.12 4.11 4.10 Name Next Page Reserved Remote Fault Reserved Asymmetric Pause Pause Description 1 = Port has ability to send multiple pages. 0 = Port has no ability to send multiple pages. Ignore. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Pause operation enabled for full-duplex links. 0 = Pause operation disabled. Type 1 R/W RO R/W R/W R/W R/W Default 0 0 0 0 0 0 1. R/W = Read/Write. RO = Read Only. 2. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to "Reset" discussion on page 22. 64 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 42. Auto Negotiation Advertisement Register (Address 4) (Continued) Bit Name Description 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available. 4.9 100BASE-T4 (The LXT9763 does not support 100BASE-T4 but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 1 = Port is 100BASE-TX full-duplex capable. 0 = Port is not 100BASE-TX full-duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T full-duplex capable. 0 = Port is not 10BASE-T full-duplex capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations should not be transmitted. R/W 0 Type 1 Default 4.8 4.7 4.6 4.5 100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T R/W R/W R/W R/W 0 Note 2 0 Note 2 0 Note 2 0 Note 2 4.4:0 Selector Field, S<4:0> R/W 00001 1. R/W = Read/Write. RO = Read Only. 2. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to "Reset" discussion on page 22. Table 43. Auto Negotiation Link Partner Base Page Ability Register (Address 5) Bit 5.15 Name Next Page Description 1 1 = Link Partner has ability to send multiple pages. 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has received Link Code Word from LXT9763. 0 = Link Partner has not received Link Code Word from the LXT9763. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 0 = Link Partner is not 100BASE-TX full-duplex capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 100BASE-TX capable. RO 0 Type 2 RO Default 0 5.14 Acknowledge RO 0 5.13 5.12 5.11 Remote Fault Reserved Asymmetric Pause Pause 100BASE-T4 100BASE-TX full-duplex 100BASE-TX RO RO 0 0 5.10 5.9 5.8 5.7 RO RO RO RO 0 0 0 0 1. Per the 1997 revision of IEEE 802.3, this register is no longer used to store Link Partner next pages. Register 8 (Table 46 on page 67) is now used for that purpose. 2. RO = Read Only. Datasheet 65 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 43. Auto Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit 5.6 5.5 Name 10BASE-T full-duplex 10BASE-T Description 1 1 = Link Partner is 10BASE-T full-duplex capable. 0 = Link Partner is not 10BASE-T full-duplex capable. 1 = Link Partner is 10BASE-T capable. 0 = Link Partner is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations shall not be transmitted. Type 2 RO RO Default 0 0 5.4:0 Selector Field S<4:0> RO 00000 1. Per the 1997 revision of IEEE 802.3, this register is no longer used to store Link Partner next pages. Register 8 (Table 46 on page 67) is now used for that purpose. 2. RO = Read Only. Table 44. Auto Negotiation Expansion (Address 6) Bit 6.15:6 Name Reserved Ignore on read. This bit indicates the status of the Auto_Negotiation variable, base page. It flags synchronization with the Auto_Negotiation state diagram allowing detection of interrupted links. This bit is only used if bit 16.1 (Alternate NP feature) is set. 1 = base_page = true. 0 = base_page = false. 6.4 6.3 6.2 Parallel Detection Fault Link Partner Next Page Able Next Page Able 1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred. 1 = Link partner is next page able. 0 = Link partner is not next page able. 1 = Local device is next page able. 0 = Local device is not next page able. 1 = Indicates that a new page has been received as and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of 802.3. This bit will be cleared on read. If bit 16.1 is set, the Page Received bit will also be cleared when mr_page_rx = false or transmit_disable = true. 1 = Link partner is auto-negotiation able. 0 = Link partner is not auto-negotiation able. RO/ LH RO RO 0 0 1 Description Type 1 RO Default 0 6.5 Base Page RO 0 6.1 Page Received RO LH 0 6.0 Link Partner A/ N Able RO 0 1. RO = Read Only. LH = Latching High. 66 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 45. Auto Negotiation Next Page Transmit Register (Address 7) Bit 7.15 7.14 7.13 7.12 Name Next Page (NP) Reserved Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Additional next pages follow. 0 = Last page. Write as 0, ignore on read. 1 = Message page. 0 = Unformatted page. 1 = Will comply with message. 0 = Can not comply with message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. Type 1 R/W RO R/W R/W Default 0 0 1 0 7.11 R/W 0 7.10:0 R/W 00000000 001 1. RO = Read Only. R/W = Read/Write Table 46. Auto Negotiation Link Partner Next Page Receive Register (Address 8) Bit 8.15 8.14 8.13 8.12 Name Next Page (NP) Acknowledge (ACK) Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Link Partner has additional next pages to send. 0 = Link Partner has no additional next pages to send. 1 = Link Partner has received Link Code Word from LXT9763 .0 = Link Partner has not received Link Code Word from LXT9763. 1 = Page sent by the Link Partner is a Message Page. 0 = Page sent by the Link Partner is an Unformatted Page. 1 = Link Partner Will comply with the message. 0 = Link Partner can not comply with the message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. User definable. Type 1 RO RO RO RO Default 0 0 0 0 8.11 RO 0 8.10:0 RO 0 1. RO = Read Only. Note: Registers 9, 10 and 15 are not implemented. These registers only have meaning for 100BASE-T2 and 1000BASE-T, neither of which are supported by this device. Datasheet 67 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 47. Port Configuration Register (Address 16, Hex 10) Bit 16.15 16.14 Name Reserved Force Link Pass Description Write as zero, ignore on read. 1 = Force Link Pass. Sets appropriate registers, state machines and LEDs to Pass condition, regardless of actual link state. 0 = Normal operation. 1 = Disable Twisted Pair transmitter. 0 = Normal Operation. 1 = Bypass Scrambler and Descrambler. 0 = Normal Operation. 1 = Bypass 4B5B encoder and decoder. 0 = Normal Operation. 1 = Disable Jabber. 0 = Normal operation. 1 = Enable Heart Beat. 0 = Disable Heart Beat. 1 = Disable TP loopback during half-duplex operation. 0 = Normal Operation. 1 = CRS deassert extends to RX_DV deassert. 0 = Normal Operation. Write as zero, ignore on read. 0 = Set RX_DV high coincident with SFD. (Strip off received preamble before sending data stream to MAC via MII.) 1 = Set RX_DV high and RXD=preamble when CRS is asserted. Write as zero, ignore on read. Write as zero, ignore on read. Write as zero, ignore on read. 1 = Enable alternate auto negotiate next page feature. 0 = Disable alternate auto negotiate next page feature. 1 = Select fiber mode for this port. 0 = Select TP mode for this port. Type 1 R/W R/W Default 0 0 16.13 16.12 16.11 16.10 16.9 16.8 16.7 16.6 16.5 16.4 16.3 16.2 16.1 16.0 Transmit Disable Bypass Scrambler (100BASE-TX) Bypass 4B5B (100BASE-TX) Jabber (10BASE-T) SQE (10BASE-T) TP Loopback (10BASE-T) CRS Select (10BASE-T) Reserved Preamble Enable (10BASE-T) Reserved Reserved Reserved Alternate NP feature Fiber Select R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1. R/W = Read /Write. Table 48. Quick Status Register (Address 17, Hex 11) Bit 17.15 17.14 17.13 17.12 17.11 Name Reserved 10/100 Mode Transmit Status Receive Status Collision Status Always 0. 1 = LXT9763 is operating in 100BASE-TX mode. 0 = LXT9763 is not operating 100BASE-TX mode. 1 = LXT9763 is transmitting a packet. 0 = LXT9763 is not transmitting a packet. 1 = LXT9763 is receiving a packet. 0 = LXT9763 is not receiving a packet. 1 = Collision is occurring. 0 = No collision. Description Type 1 RO RO RO RO RO Default 0 0 0 0 0 1. RO = Read Only. 68 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 48. Quick Status Register (Address 17, Hex 11) (Continued) Bit 17.10 17.9 17.8 Link Duplex Mode Auto-Negotiation Name 1 = Link is up. 0 = Link is down. 1 = Full-duplex. 0 = Half-duplex. 1 = LXT9763 is in Auto-Negotiation Mode. 0 = LXT9763 is in manual mode. 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. This bit is only valid when auto negotiate is enabled, and is equivalent to bit 1.5. Reserved. 1= Polarity is reversed. 0= Polarity is not reversed. 1 = Link Partner Pause capable. 0 = Link Partner not Pause capable. This bit is equivalent to bit 5.10. 17:3 17.2:0 Error Reserved 1 = Error Occurred (Remote Fault, X,Y,Z). 0 = No error occurred. Write as zero, ignore on read. RO RO 0 0 Description Type 1 RO RO RO Default 0 0 0 17.7 Auto-Negotiation Complete Reserved Polarity RO 0 17.6 17.5 RO RO 0 0 17.4 Pause RO 0 1. RO = Read Only. Table 49. Interrupt Enable Register (Address 18, Hex 12) Bit 18.15:8 18.7 Name Reserved ANMSK Write as 0; ignore on read. Mask for Auto Negotiate Complete. 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Speed Interrupt. 18.6 SPEEDMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Duplex Interrupt. 18.5 DUPLEXMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Link Status Interrupt. 18.4 18.3 LINKMSK Reserved 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Write as zero, ignore on read. R/W R/W 0 0 R/W 0 R/W 0 R/W 0 Description Type 1 R/W Default N/A 1. R/W = Read /Write. Datasheet 69 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 49. Interrupt Enable Register (Address 18, Hex 12) (Continued) Bit 18.2 18.1 Name Reserved INTEN Write as 0, ignore on read. Interrupt Enable. 1 = Enable interrupts on this port. 0 = Disable interrupts on this port. Test Interrupt. 18.0 TINT 1 = Force interrupt on MDINT. 0 = Normal operation. R/W 0 R/W 0 Description Type 1 R/W Default 0 1. R/W = Read /Write. Table 50. Interrupt Status Register (Address 19, Hex 13) Bit 19.15:8 19.7 Name Reserved ANDONE Ignore. Auto Negotiation Status. 1= Auto Negotiation has completed. 0= Auto Negotiation has not completed. Speed Change Status. 19.6 SPEEDCHG 1 = A Speed Change has occurred since last reading this register. 0 = A Speed Change has not occurred since last reading this register. Duplex Change Status. 19.5 DUPLEXCHG 1 = A Duplex Change has occurred since last reading this register. 0 = A Duplex Change has not occurred since last reading this register. Link Status Change Status. 19.4 19.3 19.2 19.1:0 LINKCHG Reserved MDINT Reserved 1 = A Link Change has occurred since last reading this register. 0 = A Link Change has not occurred since last reading this register. Write as zero, ignore on read. 1 = MII interrupt pending. 0 = No MII interrupt pending. Ignore. RO/SC RO/SC RO 0 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC N/A Description Type 1 RO Default N/A 1. R/O = Read Only. SC = Self Clearing when read. 70 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 Table 51. LED Configuration Register (Address 20, Hex 14) Bit Name Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous)5 0110 = Reserved 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status (Default) 0101 = Display Duplex Status 0110 = Reserved 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status (Default) 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status5 0110 = Reserved 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved Type 1 Default LED1 20.15:12 Programming bits R/W 0000 LED2 20.11:8 Programming bits R/W 0100 LED3 20.7:4 Programming bits R/W 0010 1. R/W = Read /Write. 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive, Activity or Isolate) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED maybe active for a brief time after loss of link. Datasheet 71 LXT9763 -- Fast Ethernet 10/100 Hex Transceiver with Full MII Table 51. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name Description 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. Type 1 Default 20.3:2 LEDFREQ R/W 00 20.1 20.0 PULSESTRETCH Reserved R/W R/W 1 0 1. R/W = Read /Write. 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive, Activity or Isolate) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED maybe active for a brief time after loss of link. Table 52. Transmit Control Register #1 (Address 28) Bit 28.15:4 Name Reserved Bandwidth Control 1 Ignore. 00 = Nominal Differential Amp Bandwidth 01 = Slower 10 = Fastest 11 = Faster 00 = 2.5ns 01 = 3.1ns 10 = 3.7ns 11 = 4.3ns Description Type2 R/W Default N/A 28.3:2 R/W 00 28.1:0 Risetime Control R/W Note 3 1. Transmit Control functions are approximations. They are not guaranteed and not subject to production testing. 2. RO = Read Only. R/W = Read/Write. 3. The default setting of bits 28.1:0 (Risetime) are determined by pins 91 and 94. Table 53. Transmit Control Register #2 (Address 30) Bit 30.15:14 30.13 30.12:0 Name Reserved Increase Driver Amplitude Reserved 1 = Increase Driver Amplitude 5% in all modes. 0 = Normal operation. Description Type R/W R/W R/W Default N/A 0 N/A 1. RO = Read Only. 72 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII -- LXT9763 5.0 Package Specifications Figure 37. LXT9763 Package Specification 208-Pin Plastic Quad Flat Package * Part Number LXT9763HC * Commercial Temperature Range (0C to 70C) Millimeters Dim D D1 Min A A1 A2 e Max 4.10 3.60 0.27 30.90 28.30 30.90 28.30 .50 BASIC 0.25 3.20 0.17 30.30 27.70 30.30 27.70 b D D1 e E1 E /2 E E1 e L 0.50 1.30 REF 0 5 5 0.75 2 L1 A A2 A1 L b 3 L1 q 7 16 16 2 3 Datasheet 73 |
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